FPGA Logic Cell Conversion Ratios

Published on Author Kelly Timko

SEER-IC uses the Field Programmable Gated Array (FPGA) work element to determine the recurring and non-recurring costs of developing a FPGA; it calculates all costs associated with developing HDL, verification, synthesis and test. Logic Cells are used as a key design sizing input for this work element; System Gates or Logic Elements can be used as an alternative for Logic Cells. Not all FPGA vendors define their FPGAs the same way; Slices and Adaptive Logic Modules (ALM) are also commonly used.